This invention relates to programmable logic integrated circuit devices, and more particularly to the interconnection circuitry used in such devices. Examples of known programmable logic devices (“PLDs”) are shown in Cliff et al. U.S. Pat. Nos. 5,909,126 and 5,963,049.
PLDs typically include large numbers of regions of programmable logic and other resources such as memory, input/output circuits, etc., that are selectively interconnectable via programmable interconnection resources on the device. For example, each region of programmable logic on a PLD may be programmable to perform any of several relatively simple logic functions on several input signals applied to that region in order to produce one or more output signals indicative of the result of performing the selected logic function(s) on the input signals. The interconnection resources are programmable to convey signals to, from, and between the logic regions in any of a wide variety of patterns or configurations. For example, the interconnection resources may be used to concatenate several logic regions so that much more complex logic tasks can be performed than any one logic region can perform.
It is now typical to use a single conductor for each individual interconnection pathway or path segment in PLDs. Single NMOS pass gates (controlled by programmable memory elements or circuits on the PLD) are used for selectively interconnecting each conductor to other conductors to provide various signal routings through the interconnection resources of the device.
One trend in the design of PLDs is toward the use of lower power supply voltage and therefore lower internal signaling voltage. At lower power supply voltage the Vt drop of NMOS pass gates becomes a more significant fraction or percentage of the power supply voltage. This can lead to several problems in conventional PLD interconnection circuitry. For example, signaling slows down and the circuitry becomes increasingly susceptible to capacitive cross-talk between parallel conductors.